The present invention relates to a flash memory device, and more particularly, to a method for improving the cell distribution characteristics of a non-volatile memory device (e.g., NAND flash memory device).
A flash memory device includes memory cells connected in series by adjacent memory cells sharing a source and drain. In this case, the string of memory cells is connected to a bit line. The memory cell is a transistor with a floating gate and a control gate.
A drain of the memory cell is connected to the bit line through a select gate, and a source of the memory cell is connected to a source line through a select gate. In addition, the control gates of the memory cells are disposed in sequence across the cell strings, and so a word line is formed.
Hereinafter, an operation of this NAND flash memory device will be described in detail.
An operation of writing data is performed in sequence from a memory cell that is provided farthest from the bit line.
A high voltage Vpp is applied to a control gate of a selected memory cell, and a medium voltage is applied to a control gate and a select gate of a memory cell located at the side of the bit line. Additionally, 0V or the medium voltage is applied to the bit line in accordance with a program data.
When 0V is applied to the bit line, the voltage of 0V is provided to the drain of the selected memory cell, and so electrons are injected from the drain to the floating gate. As a result, a threshold value of the selected memory cell is shift in a positive direction.
Further, an erase is performed simultaneously in every memory cells in the same block of the NAND flash memory device. That is, a high voltage is applied to the P-type well and the N-type substrate under the condition that 0V is applied to every control gate and select gate, and the bit line and the source line are in a floating state. As a result, for the memory cells in the block, electrons in the floating gates are emitted to the P-type well, and so the critical value is shift in a negative direction.
An operation of reading data is performed by detecting whether or not current is passed through the selected memory cell when 0V is applied to the control gate of the selected memory cell and a power supply voltage is provided to a control gate and a select gate of the other memory cells.
FIG. 1 is a view illustrating common cell distribution characteristics. FIG. 2 is a view illustrating the change of threshold voltage of a cell in accordance with the increase of a program voltage.
FIG. 1 shows the cell distribution characteristic of a multi-level cell for storing data of 2 bits. Here, the cell distributions are separated into a first state St1 (not programmed) and second to fourth states St2 to St4 (programmed).
Generally, the first state St1 is assigned to data ‘00’, the second state St2 to data ‘01’, the third state St3 to data ‘11’, and the fourth state St4 to data ‘10’.
Read voltages RD1, RD2 and RD3 are applied so as to read data in accordance with each of the cell distributions, and verifying voltages PV1, PV2 and PV3 are applied when a program verify is performed.
A shift phenomenon can occur in the multi-level cell flash memory device having the above cell distributions if it performs in sequence a program operation, a read operation and an erase operation. As a result, the threshold voltages may be changed as shown in the dotted line of FIG. 1.
This phenomenon is referred to as a “cell voltage shift phenomenon” or “threshold voltage shift phenomenon”. Data integrity becomes low in a case where the memory cell is maintained at a data program state for a long time, and so the cell distribution becomes wide. In particular, cell characteristics of cells having bad program characteristics is deteriorated.
As shown in FIG. 2, the cell voltage shift phenomenon increases as a program verify voltage level is increased. The cell voltage shift phenomenon also increases when an operation cycle is increased. An operation cycle of a dotted line 220 is longer than an operation cycle of a solid line 210. Accordingly, to program these cells, a higher voltage would be required, and the duration of a program time would need to be increased.